DocumentCode
507136
Title
Notice of Retraction
Real-time Data Storage Research Based on RAM
Author
Zhang Yan ; Liu Wenyi
Author_Institution
Electron. & Comput. Sci. Technol. Coll., North Univ. of China, Taiyuan, China
Volume
1
fYear
2009
fDate
13-15 Nov. 2009
Firstpage
359
Lastpage
362
Abstract
Notice of Retraction
After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE´s Publication Principles.
We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.
The presenting author of this paper has the option to appeal this decision by contacting TPII@ieee.org.
The use of FPGA internal RAM can be an effective alternative to external FIFO, using the method OF Programming FOR the FPGA, Make full use of FPGA internal resources that provided strong support For the realization of a programmable system chip (SOPC, SystemOn Programable Chip). It Effected reducing the use of devices and minimizing the circuit boards. Acquisition and storage respectively controlled by two FPGA chips in this study. Use their own internal RAM, program variety controlling models by VHDL hardware language. And then connect the internal schematic to replace the external FIFO. This is the internal FIFO of FPGA.
After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE´s Publication Principles.
We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.
The presenting author of this paper has the option to appeal this decision by contacting TPII@ieee.org.
The use of FPGA internal RAM can be an effective alternative to external FIFO, using the method OF Programming FOR the FPGA, Make full use of FPGA internal resources that provided strong support For the realization of a programmable system chip (SOPC, SystemOn Programable Chip). It Effected reducing the use of devices and minimizing the circuit boards. Acquisition and storage respectively controlled by two FPGA chips in this study. Use their own internal RAM, program variety controlling models by VHDL hardware language. And then connect the internal schematic to replace the external FIFO. This is the internal FIFO of FPGA.
Keywords
field programmable gate arrays; logic design; programmable logic devices; random-access storage; system-on-chip; FPGA internal RAM; FPGA internal resources; OF Programming; System-On-Programmable Chip; VHDL hardware language; programmable system chip; real-time data storage; Central Processing Unit; Clocks; Consumer electronics; Field programmable gate arrays; Hardware; Logic devices; Pins; Programmable logic arrays; Random access memory; Read-write memory; FIFO; RAM; RAM address bits; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Technology and Development, 2009. ICCTD '09. International Conference on
Conference_Location
Kota Kinabalu
Print_ISBN
978-0-7695-3892-1
Type
conf
DOI
10.1109/ICCTD.2009.36
Filename
5359690
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