A variation-aware preferential design approach for memory based reconfigurable computing

Static random access memory (SRAM) arrays designed in sub-90 nm technologies are highly vulnerable to process variation induced read/write/access failures. In memory based reconfigurable computing frameworks, which use large high density memory array, such failures lead to incorrect execution of mapped applications. It causes loss in quality of service (QoS) for digital signal processing (DSP) applications. We propose a ¿preferential design¿ approach at both application mapping and circuit level, which can significantly improve QoS and yield under large parameter variations. Such a architecture/circuit co-design approach can also tolerate increased failure rate at low operating voltage, thus facilitating low-power operation. Simulation results for a common DSP application show 45% improvement in power at iso-QoS and 47% in yield for a target peak signal to noise ratio (PSNR) at 45 nm technology.