Redesigned CMOS (4; 2) compressor for fast binary multipliers

(4; 2) compressors seem to be the most popular bit-compressing cells with principal application in multi-operand addition and multiplication hardware. Therefore, performance of (4; 2) compressors is particularly influential in the efficiency of multiplication intensive computations. Realization of these cells is mainly based on XOR/XNOR gates, which are functionally equivalent to three simpler ones among AND/NAND and OR/NOR gates. Decomposition of XOR/XNOR gates in some (4; 2) compressors to their constituent simpler ones may lead to removal of some hardware redundancy. In this paper we take advantage of such decomposition to propose a new (4; 2) compressor design, evaluate its performance, and compare it with previous designs. The proposed (4; 2) compressor, as such, and those of reference works are simulated with HSPICE using 45nm post-layout CCMOS standard cell library with presence of process variation. The results show performance improvements, compared to the best of reference designs, in terms of delay (17%), power (13%), and power-delay-product (30%). For more realistic comparison, performance of each design is evaluated via incorporation of more than 1300 (4; 2) compressors in 54×54-bit binary multipliers as a uniform test bench via MAGMA tools. This experience confirmed the above results on isolated single (4; 2) compressors.