Research on the Parallelism of Security Vulnerability Detection of Logic-Unknown PLD

As the development of integrated circuit, the algorithms of security vulnerability detection available are not suitable for encrypted PLD in large scale, which would bring in acceptable consumption of memory and time. By analyzing the relation of input signals and output signals of the sequential logic circuit, the parallelism of state saturating and the parallelism between CPU and detection platform in vulnerability detection is digged out. Based on the parallelism, the model for parallel detection is proposed, which saturates state and searches the path for state transition on several detection equipments. The model makes full of resources of equipments, solves the problem that the memory is not enough to establish state transition diagram and reduces the time needed for vulnerability detection effectively.