A crosstalk minimization technique for sublithographic programmable logic arrays

The emergence of alternative technologies due to continued technology migration into the nanometer regime has led to the design of several novel logic and memory architectures. These architectures, in particular array based architectures built from crossbar structures, aim to achieve higher logic/memory densities with lower power consumption and acceptable delays as compared to present day CMOS technology. However crosstalk induced in these nanoscale arrays limits the minimum wire spacing realizable and thereby the logic density that can be achieved. In this work we analyze the crosstalk produced in sublithographic programmable logic array (PLA) architectures and propose an alternative layout scheme that reduces the effects of crosstalk in adjacent wires. The proposed methodology has an interleaved layout scheme with two non-overlapping out-of-phase clocks that prevent neighboring wires from transitioning simultaneously. Results presented in this paper indicate that this scheme provides for better tolerance against crosstalk than other structures proposed for sublithographic PLAs. The effects of different parasitics (i.e. coupling and decoupling capacitances from different parts of the crossbar segment) on the crosstalk induced are also analyzed.