Influence of gate architectures on the performance of SOI MOSFETs including the strained channel

Author

Bhattacherjee, Swagata ; Biswas, Abhijit ; Basu, P.K.

Author_Institution

Dept. of Radio Phys. & Electron., Univ. of Calcutta, Kolkata, India

fYear

2009

fDate

14-16 Dec. 2009

Firstpage

1

Lastpage

4

Abstract

In this paper, general analytical models for threshold voltage V_t and subthreshold slope S of single gate (SG), symmetric double gate (DG) and ground plane (GP) MOSFETs are proposed. The effect of channel strain on V_tÂ¿ S and drain induced barrier lowering (DIBL) is also investigated. The proposed model has been employed to calculate V_tÂ¿ S and DIBL for various MOS structures. Additionally simulation has been performed using ATLAS, a 2D numerical device simulator. Accuracy of models has been verified by comparing analytical results obtained from proposed models with the simulated data and a few reported experimental results.

Keywords

MOSFET; semiconductor device models; silicon-on-insulator; 2D numerical device simulator; ATLAS; MOS structures; SOI MOSFETs; channel strain; drain induced barrier lowering; general analytical models; ground plane MOSFETs; single gate MOSFETs; subthreshold slope; symmetric double gate MOSFETs; threshold voltage; Analytical models; Boundary conditions; Capacitive sensors; Computational modeling; Computer architecture; MOS devices; MOSFETs; Physics; Poisson equations; Threshold voltage; DG MOSFETs; DIBL; GP MOSFETs; subthreshold slope; threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Computers and Devices for Communication, 2009. CODEC 2009. 4th International Conference on

Conference_Location

Kolkata

Print_ISBN

978-1-4244-5073-2

Type

conf

Filename

5407106