Power, delay and noise optimization of a SRAM cell using a different threshold voltages and high performance output noise reduction circuit

Nowadays there is a strong demand for higher speed, low leakage, low power and low noise SRAM cell to develop a high speed memory. In this paper conventional 6T SRAM has been replaced by a 8T SRAM circuit. The access transmission gates (access TG 1 & access TG 2, shown in Fig 2) have been used instead of simple pass transistors to reduce leakage current. The lower power consumption, lower leakage power consumption, lower delay and lower noise has been achieved by applying dual threshold voltage technology and the advanced output noise reduction circuit. Here we have used separate read and write lines considering that their compliment is also available to make the read and write operations mutually exclusive. I have used TG to transfer data to output in read operation so that both logic low and high can be transferred well. By using output noise reducing circuit I develop the very low noise at the output of a 8T SRAM, where the noise is optimized.