The 1/f Noise Behaviour of Interface Engineered Polysilicon Emitter Bipolar Transistors

This paper discusses the impact of interfacial layer engineering on the low-frequency noise behaviour of polysilicon emitter bipolar transistors. The main purpose of the interface engineering is to tailor the DC parameters (current gain ß). However, it will be shown that if the base-emitter junction depth is not varied too much, this engineering also determines the noise of the transistors, for sufficiently large base currents. This is a consequence of the experimentally found linear relationship between ß and the noise. Finally, the impact of the observed noise behaviour for practical circuit operation will be discussed.