Self-Isolated LDMOS and Bi-nMOS Power Transistors Implemented by CMOS Process Technology

This paper details the process features, device design and electrical characteristics for the lateral DMOS(LDMOS) and Bi-nMOS power devices that were implemented by the conventional 1.2¿m, double metal CMOS process technology. The power devices, which were fabricated by the non-epi, self-isolation structure, allow the full compatibility with low-voltage analog/digital CMOS circuits on the same chip. Through proper optimization of LDMOS, a specific on-resistance of 0.4m¿-cm² has been achieved. Another Bi-nMOS device, based on a merged bipolar-MOS concept, exhibits over ten times higher current driving capability than LDMOS under the same applied voltage.