Investigation and Suppression of the Gate Disturb Effect in Source-Side Injection Flash EEPROM Arrays

Most Flash memories rely on channel hot-electron injection or on Fowler-Nordheim tunnelling for programming. However, Source-Side Injection (SSI) has also been suggested as an alternative programming mechanism since it combines a high injection efficiency with a low power consumption^1-6). In the meanwhile, the viability of using this programming mechanism for state-of-the-art nonvolatile applications has been sufficiently demonstrated and the ability to establish fast programming from a single supply voltage has been a driving force for the further qualification of SSI devices^5-8). When implementing these novel device structures in memory arrays, the influence of disturb effects in the different operating modes has to be investigated and subsequently minimized by technological or design solutions. Indeed, the outcome of such a disturb analysis is not only a function of the cell structure and of the operating voltages, but also of the array architecture^6-8). Particularly for embedded memory applications, technological changes should be avoided in order to maintain a high cost-effectiveness. This paper reports on a critical gate disturb effect in split-gate SSI cells for embedded applications. Different interpoly isolation schemes have been investigated and it is shown that sufficient disturb margin is obtained without major changes to the process flow.