Influence of Tunnel Effects on C-V Curves in Amorphous Silicon Devices

The tunnelling phenomena inside the amorphous silicon MOS devices are not only responsible for the turn-off leakage currents; the alteration in the stored charge distribution due to the tunnel-generated carriers is also expected to modify the values of the turn-off capacitances. Simulations based on the mathematical model illustrated in this work predicts for the gate-to source turn-off capacitance a strongly different behaviour in presence and in absence of tunnel generations, providing a physical interpretation of this difference.