DocumentCode
513974
Title
Self-Aligned Technology for Sub-100nm Deep Base Junction Transistors
Author
Nakamae, Masahiko
Author_Institution
1st LSI Division, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa, Japan
fYear
1987
fDate
14-17 Sept. 1987
Firstpage
361
Lastpage
363
Abstract
The problems in scalling down of modern advanced polysilicon self-aligned transistors are brief1y discussed. Then, a novel self-aligned technology is proposed to solve the problems. The newly developed BSA (BSG Self-Aligned ) technology is featured by the use of CVD-BSG Film as a sidewall spacer as well as a diffusion source to form both intrinsic base and p+-connecting regions, simultaneousely. The fabricated transistor having 40nm deep emitter-base junction and sub-100nm collector-base junction shows 70 of hFE and 7V of BVCEO , respectively.
Keywords
Annealing; Boron; Capacitance; Doping; Etching; Joining processes; Large scale integration; National electric code; Space technology; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1987. ESSDERC '87. 17th European
Conference_Location
Bologna, Italy
Print_ISBN
0444704779
Type
conf
Filename
5436586
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