Isolation - Related Leakage in a 4 Mb DRAM Cell

The isolation-related leakage occurring within a 4 Mb DRAM cell containing a depletion-type trench capacitor is discussed. The main isolation-dependent leakage paths discussed are trench-trench punchthrough, inter-bit-line leakage via punchthrough or parasitic transistor action under the word-line, and leakage between the transfer gate and the trench capacitor. Measurements of specific test structures and also of an 8K cell array confirming good control of these leakage mechanisms are presented.