• DocumentCode
    514097
  • Title

    Comparison of 11.5 μm2 Stacked Capacitor and Trench Capacitor Cells in Mbit Test Mnmory

  • Author

    Risch, L. ; Sesselmann, W. ; Tielert, R.

  • Author_Institution
    Siemens AG, Central Research and Development, ME23, Otto Hahn Ring 6, 8 Munich 83, FRG
  • fYear
    1987
  • fDate
    14-17 Sept. 1987
  • Firstpage
    757
  • Lastpage
    760
  • Abstract
    A 1Mbit DRAM testcircuit with stacked capacitor or alternatively with trench capacitor cells has been fabricated in 4Mbit design rules and technology. The smaller capacitances obtained by the stacked capacitor at same cell sizes is compensated by reduced leakage currents and α-particle sensitivity. Both cells need a cell voltage of 5V for reliable operation.
  • Keywords
    Capacitance; Capacitors; Dielectrics; Doping; Geometry; Leakage current; Random access memory; Testing; Topology; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference, 1987. ESSDERC '87. 17th European
  • Conference_Location
    Bologna, Italy
  • Print_ISBN
    0444704779
  • Type

    conf

  • Filename
    5436745
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=514097