DocumentCode
514147
Title
Scalling of Trench Capacitor Cell for Next Generation DRAMs
Author
Mühlhoff, H.M. ; Rogers, C.M. ; Murkin, P. ; Elahy, M. ; Rohl, S.
Author_Institution
Siemens AG, Corporate Research and Technology, Otto-Hahn-Ring 6, D-8000 Munchen, F.R.C.
fYear
1988
fDate
13-16 Sept. 1988
Abstract
When scaling a trench capacitor cell developed for the 4Mbit DRAM further down, both process and device limits are encountered. Device related topics are the subject of this paper. Issues to be discussed are: (1) narrow width effects of pass transistors, (2) short channel effects, (3) effect of storage region on pass transistor, (4) isolation between neighbouring cells.
Keywords
Capacitors; Degradation; Doping; Electrons; Implants; Random access memory; Stress; Threshold voltage; Transistors; Varactors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1988. ESSDERC '88. 18th European
Conference_Location
Montpellier, France
Print_ISBN
2868830994
Type
conf
Filename
5436959
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