Limitations on n*/p* Spacing Due to Shadowing Effects in a 0.7μm Retrograde Well CMOS Process

Use of high energy ion implantation for retrograde wells requires thick resist layers to prevent implant penetration. Shadowing of the n-well implant results in a displacement in the position of the n-well edge, dependent on the position across the wafer and implant angle, thereby requiring a larger minimum design rule. Electrical measurement of n⁺/n-well field transistors as a function of spacing and orientation has been used to investigate the amount of shadowing which occurs for nominal 7° implants. Shadowing effects were found to vary from 0.15 to 0.25μm across a typical 4 inch diameter wafer.