2-D and 3-D Capacitance Effects in MOS VLSI

Spreading capacitances of several MOS VLSI configurations have been calculated numerically by solvincg Poisson´s equationi in 2 or 3 dimensions. Owing to nonuniform charge distributions, contributions from sidewalls and topsurfaces, and shielding effects, considerable deviations from scarce analytic formula have been found. Successively considered are the cases: 3 parallel conductors at equal height from the substrate, 2 parallel conductors at different level from the substrate, gate-drain configuration of different MOSFETs, and two conductors or four conductors crossing above a substrate.