A New Type of High Performance Device for VLSI Digital System

This paper presents a high performance Complementary Buried Channel FET device isolated by high quality silicon dioxide layer using Silicon wafer Direct Bonding technology (SDB/CBCFET). The structure and operational principle of this device is discussed. The properties of an improved SDB process is investigated. By means of 2D numerical simulation, effects of interface charge density of bonding interface and SOI layer-SiO2 interface on threshold voltage and the threshold voltage shift in submicron geometry are analysed. The performance of submicron SDB/CBECET device and circuits is evaluated. The results indicate that SDB/CBCFET device is superior to bulk CMOS and SOI/CMOS in speed, switching energy, complexity, reliability and small size effects as device size decreases into submicron dimension.