Optimization of Nitridation Conditions for High Quality Inter-Polysilicon Dielectric Layers

Nitridation of deposited high temperature oxides (HTO) was studied to form high quality inter-polysilicon dielectric layers for embedded non volatile memories. Good quality dielectric layers were obtained earlier by using an optimized deposition of polysilicon and by performing a post-dielectric anneal in a rapid thermal processor. In the present paper the quality is further improved by means of optimization of the post-dielectric anneal. The influence of temperature, time and pressure during annealing on the electrical properties is investigated. Electrical characterization by means of charge-to-breakdown (Qbd) and I-V measurements on simple capacitor structures evaluates the electrical properties of the layers. It is shown that an (optimized) rapid thermal N2O anneal leads to a very high charge to breakdown (Qbd ¿ 25 C/cm²), low charge trapping and low leakage currents.