DocumentCode
516003
Title
Implementation of high-speed buffer management for asynchronous variable-length optical packet switch
Author
Furukawa, Hideaki ; Harai, Hiroaki ; Ohta, Masataka ; Wada, Naoya
Author_Institution
Nat. Inst. of Inf. & Commun. Technol., Tokyo, Japan
fYear
2010
fDate
21-25 March 2010
Firstpage
1
Lastpage
3
Abstract
We develop an FPGA-based buffer management hardware with 8 input ports, which implements a parallel and pipeline mechanism to support over-200-Mpacket/s/port asynchronous variable-length optical packet switching. Optical buffering for asynchronous variable-length packets is demonstrated.
Keywords
buffer circuits; field programmable gate arrays; optical switches; packet switching; FPGA-based buffer management hardware; asynchronous variable-length optical packet switch; high-speed buffer management; optical buffering; Control systems; Electric variables control; High speed optical techniques; Optical buffering; Optical control; Optical modulation; Optical packet switching; Optical switches; Optical variables control; Pipelines;
fLanguage
English
Publisher
ieee
Conference_Titel
Optical Fiber Communication (OFC), collocated National Fiber Optic Engineers Conference, 2010 Conference on (OFC/NFOEC)
Conference_Location
San Diego, CA
Electronic_ISBN
978-1-55752-884-1
Type
conf
Filename
5465717
Link To Document