A Robust Analog Two Phase On-Chip Clock Generator

In this paper the problem of generating on-chip two phase non-overlapping clocks for the Cathedral Silicon Compiler Environment is discussed. The problem is made harder by the introduction of robustness requirements, which means that the steady state response of the generator has to be maintained regardless of power supply, temperature, process variations, noise and even harder, scaling and technology up dates. It is worth stressing that we have developed a structure can be scaled (λ scaling) and can be processed by different foundries without a significant change in the I/O steady-state response because of the adaptive feedback principles. We show that the problem has a solution capable of handling such adverse constraints. We use the concept of a flexible operating point as the driver of the design.