DocumentCode
516157
Title
A 2.5 Gb/s GaAs Clock and Data Regenerator I.C.
Author
Ransijn, Hans ; Connor, Paul O.
Author_Institution
AT&T Bell Labs., Reading, PA, USA
Volume
1
fYear
1990
fDate
19-21 Sept. 1990
Firstpage
217
Lastpage
220
Abstract
A GaAs IC that performs clock and data regeneration functions for high speed fiber optic transmission systems is presented. This IC, in conjunction with a companion Si bipolar chip, can regenerate pseudo random NRZ data at rates up to 2.5 Gb/s with a sensitivity of 15 mV and uses a single -5.2 V ECL compatible power supply.
Keywords
III-V semiconductors; clock and data recovery circuits; elemental semiconductors; field effect integrated circuits; frequency locked loops; gallium arsenide; phase locked loops; silicon; ECL compatible power supply; GaAs; Si; bipolar chip; bit rate 2.5 Gbit/s; clock and data regenerator integrated circuit; frequency locked loops; high speed fiber optic transmission systems; phase locked loops; pseudo random NRZ data regeneration; Circuit testing; Clocks; Delay; Detectors; Gallium arsenide; Optical amplifiers; Phase detection; Photonic integrated circuits; Repeaters; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European
Conference_Location
Grenoble
Print_ISBN
2-86332-087-4
Type
conf
Filename
5467731
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