A Prototype Programmable Digital LDI Filter Circuit

A prototype chip implementing a 7-th order pole-zero low-pass digital LDI ladder filter with programmable coefficients has been fabricated in 1μ CMOS technology. Its complexity is 17000 transistors, with an area of 3 mm². This circuit was designed as a test vehicle for a fully integrated VLSI function compiler, that takes as input the frequency specifications of a filter. New and unique LDI structures are used, which are especially well suited to this design approach : their excellent properties with respect to finite arithmetic effects result in optimum hardware complexity, while their modularity and regularity lead to a very simple placement and densely packed layout, with minimal routing overhead. The bit-serial systolic architecture adopted allows to operate up to 50 MHz.