Title :
Key Circuit Techniques for a High-Speed, Low-Power Psram using the BICMOSG3 Cell for Storage Array
Author :
Matzke, W.-E. ; Winkler, W. ; Richter, R. ; Perbandt, A. ; Pregel, J.
Author_Institution :
Inst. for Phys. of Semicond., Frankfurt (Oder), Germany
Abstract :
This paper describes the architecture and key circuit techniques of a PSRAM using the BiCMOSG3 cell for storage array. The important features of the cell from the circuit techniques point of view are reported. An inverting refresh scheme resulting in a very simple refresh circuitry is proposed. The functional separation between refresh amplifiers and sense amplifiers for selective access operations permits very fast access operations. A 16-kbit test memory was designed as a part of a 1-Mbit PSRAM concept. The delay time in the storage array is 4 ns.
Keywords :
BiCMOS memory circuits; SRAM chips; amplifiers; low-power electronics; memory architecture; BiCMOSG3 cell; PSRAM concept; architecture; delay time; functional separation; high-speed PSRAM; inverting refresh scheme; key circuit techniques; low-power PSRAM; refresh amplifiers; refresh circuitry; selective access operations; sense amplifiers; storage array; test memory; BiCMOS integrated circuits; CMOS technology; Circuit simulation; Circuit testing; Delay effects; Operational amplifiers; Random access memory; Timing; Voltage; Writing;
Conference_Titel :
Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European
Conference_Location :
Grenoble
Print_ISBN :
2-86332-087-4
