DocumentCode
516188
Title
A Self Testing 2 Micron CMOS Chip Set for FFT Applications
Author
Fox, J. ; Surace, G. ; Thomas, P.A. ; MacAulay, I.A.
Author_Institution
Plessey Research (Caswell) Ltd., Caswell, Towcester, Northants, England, NN12 8EQ.
fYear
1985
fDate
16-18 Sept. 1985
Firstpage
13
Lastpage
24
Abstract
A chip set for high speed radix-2 FFT applications up to 512 points is described. The chip set comprises a (16+16)*(12+12) bit complex multiplier; and a 16 bit butterfly chip for data re-ordering, twiddle factor generation and butterfly arithmetic. The chips have been implemented using the Megacell design methodology on a 2 micron bulk CMOS process. Three chips implement a complex FFT butterfly with a throughput of 10MHz, and are cascadable up to 512 points. The chips feature an off-line self testing capability.
Keywords
Arithmetic; Automatic testing; CMOS process; Hardware; Logic arrays; Pipelines; Read only memory; System testing; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European
Conference_Location
Toulouse, France
Type
conf
Filename
5467769
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