On the Physical Design of Testable CMOS Digital Circuits

VLSI design productivity quests for an efficient design system, incorporating testability features. Usually, design for testability (DFT) techniques are applied down to the logic design level, and test patterns are generated to cover single line stuck-at (LSA) faults. However, for CMOS technologies, this fault model is not sufficiently accurate. In this paper, a methodology for extending and assessing testability down to the layout level is presented, together with a set of software tools that implement it. The concepts of weighted class fault coverage and fault incidence are introduced, as measures of physical testability. The testability is evaluated, prior to fault simulation. Layout-level testability design rule checking is carried out, and suggestions for layout reconfiguration are provided. Several design examples are described, ascertaining the usefulness of the proposed methodology.