A Flexible Boundary Scan Implementation in a Silicon Compiler Environment

Author

Lestrat, P. ; Leveugle, R.

Author_Institution

Thomson Composants Militaires et Spatiaux, St. Egreve, France

Volume

1

fYear

1990

fDate

19-21 Sept. 1990

Firstpage

113

Lastpage

116

Abstract

This paper reviews the design carried out to implement the IEEE P1149.1 boundary scan standard in the TSBC3 compiled portable library based on the GDT®/GENESIL® tools. The advantage of this compiled approach is to provide a flexible set of boundary scan cells, including pads and Test Access Port (TAP) controllers. The boundary scan register is automatically assembled while creating the pad ring and different parameterized function complexities allow to easily dedicate the TAP controller to any application. The cost of boundary scan integration has shown to be reasonnable in comparison with the ease of board testing.

Keywords

boundary scan testing; electronic engineering computing; integrated circuit testing; board testing; boundary scan cell; boundary scan integration; compiled portable library; flexible boundary scan register; parameterized function complexity; silicon compiler environment; test acess port controllers; Application specific integrated circuits; Assembly; Automatic control; Costs; Electronic equipment testing; Libraries; Logic testing; Power supplies; Semiconductor device testing; Silicon compiler;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European

Conference_Location

Grenoble

Print_ISBN

2-86332-087-4

Type

conf

Filename

5467772