Clock Distribution in High Speed A/D Converters

This paper describes a clock interface suitable in the high speed monolithic bipolar A/D converters. It is based on two main cells. An input buffer drives in a fully symmetrical manner capacitive loads with an optimal slew rate. Then, an adjustable delay circuit gives flexibility in the delay matching around the circuit. This interface implemented in a 7 Ghz bipolar process drives capacitive loads of 20 to 30 pF for clock frequency over 100MHz with 40mW power consumption.