Optimization of Buffer Stages in Bipolar VLSI Systems

This work deals with the optimization of the following buffer stages used in ECL and Cascode ECL VLSI systems: a) the level shifters (including the pure emitter follower) and b) the Darlington configuration. Analytical delay expressions for all these buffer stages have been extracted considering high speed operation. In addition, the optimum bias current(s) achieving the minimum power-delay product have been determined. The same delay expressions apply also to BiCMOS buffers. The expressions extracted combine simplicity and accuracy leading to a fast optimization procedure.