DocumentCode
516238
Title
A Unified Theory for Mixed CMOS / BiCMOS Buffer Optimization
Author
Sakurai, Takayasu
Author_Institution
Semiconductor Device Eng. Lab., Toshiba Corporation, 1 Komukai-Toshiba-cho, Saiwai-ku, Kawasaki, 210, Japan. Phone: +81-44-549-2203 FAX: +81-44-555-2074
Volume
1
fYear
1991
fDate
11-13 Sept. 1991
Firstpage
129
Lastpage
132
Abstract
A simple yet realistic gate sizing theory is presented to optimize delay of a cascaded gate buffer. The theory is based on the fact that CMOS / BiCMOS gate delay is linearly dependent on fanout f, that is, the delay can be expressed as Af + B, where A and B are coefficients. The optimum fanout fOPT is shown to be approximated as e+B/1.5A for a gate chain. The theory covers various BiCMOS / CMOS gate types such as NAND´s and NOR´s in a unified framework.
Keywords
BiCMOS integrated circuits; Capacitance measurement; Delay lines; Design automation; Inverters; MOSFET circuits; Optimized production technology; SPICE; Semiconductor devices; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1991. ESSCIRC '91. Proceedings - Seventeenth European
Conference_Location
Milan, Italy
Type
conf
Filename
5467831
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