A Configurable Convolution Chip with Programmable Coefficients

This paper describes the architecture and implementation of a bit-level configurable convolver array. The systolic field supports configuration during operation in number of taps and coefficient word length. A chip has been designed in 1.5 ¿m CMOS using full custom design style which contains 112000 transistors on an active area of 45 mm². The configurability consumes only 9% of that area. 50 MHz operating speed is expected from simulation. First test results have been obtained. An extension of the architecture for optimised calculation of transformations is also presented.