DocumentCode :
516283
Title :
A Single-Chip 9-32 Mbit/s Read/Write Channel for Disk-Drive Applications
Author :
Zuffada, M. ; Alini, R. ; Colletti, P. ; Demicheli, M. ; Gregori, M. ; Moloney, D. ; Portaluri, S. ; Sacchi, F. ; Arf, S. ; Condito, V. ; Castello, R.
Author_Institution :
SGS-Thomson Microelectronics, via C. Olivetti 2, Agrate Brianza, Italy
Volume :
1
fYear :
1993
fDate :
22-24 Sept. 1993
Firstpage :
234
Lastpage :
237
Abstract :
This paper reports on a single-chip read/write channel for disk drive. The integrated circuit implements a peak detector architecture fully compatible with zoned-bit recording applications. The chip contains all the functions needed to implement a high performance read channel like pulse detector, programmable active filter, servo demodulator, frequency synthesizer and data separator. The design take fully advantage of the feature available in a BICMOS technology to achieve power saving, high speed and immunity to cross-talk from digital to analog. The IC is fabricated in a 1.2 ¿m BiCMOS technology and has an active area of approximately 28 mm2. While operating from a single 5 V supply the power consumption is only 450 mW at 32Mbit/s.
Keywords :
Active filters; Application specific integrated circuits; BiCMOS integrated circuits; Demodulation; Detectors; Disk drives; Disk recording; Frequency synthesizers; Particle separators; Servomechanisms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1993. ESSCIRC '93. Nineteenth European
Conference_Location :
Sevilla, Spain
Print_ISBN :
2-86335-134-X
Type :
conf
Filename :
5467887
Link To Document :
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