• DocumentCode
    516286
  • Title

    A Versatile Digital CMOS Video Delay Line with Embedded ADC, DAC and RAM

  • Author

    Vertregt, M. ; Dijkstra, M.B. ; van Rens, A.C. ; Pelgrom, M.J.M.

  • Author_Institution
    Philips Research Laboratories, P.O. Box 80000, 5600JA Eindhoven, The Netherlands
  • Volume
    1
  • fYear
    1993
  • fDate
    22-24 Sept. 1993
  • Firstpage
    226
  • Lastpage
    229
  • Abstract
    A video line compression chip is presented which can change the aspect ratio of PAL and NTSC video pictures into a multitude of formats. It has analog input and output and contains embedded AD, DA, 18Kbit SRAM, control and configuration logic. This has the advantage that switching-noise generating digital I/O´s are absent. Experimental results show that spurious components are below -50dB of the applied fundamental. The chip was fabricated in a high volume 1¿m full CMOS process and operates at 54 MHz maximum clockrate.
  • Keywords
    Abstracts; Delay lines; Solid state circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1993. ESSCIRC '93. Nineteenth European
  • Conference_Location
    Sevilla, Spain
  • Print_ISBN
    2-86335-134-X
  • Type

    conf

  • Filename
    5467890
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516286