New LSI Architecture for Ultra-High-Speed Error Correction and its Application to the Majority Decoding LSI for (1057,813) Code

An ultra-high-speed error correction method for difference-set cyclic codes of longer code length has been developed that introduces pipeline architecture into the inner feedback loop of the decoding circuit and avoids the propagation of erroneous data during latency. The new architecure can in principle raise the operation speed of the error correction chip to the toggle frequency of the syndrome register. Based on this architecture, a majority decoding chip for (1057,813) difference-set cyclic code has been fabricated using our experimental 2 ¿m CMOS technology. It contains about 12k gates and operates at 30 MHz clock-rate.