An Experimental 1.8 μm CMOS Anti-Aliasing Switched-Capacitor Decimator with High Input Sampling Frequency

An optimum anti-aliasing switched-capacitor (SC) decimator is capable of achieving a high input sampling ratio while employing operational amplifiers operating at a much lower frequency than what would be needed in conventional SC filtering circuits. This is demonstrated considering the design of a 2nd. order SC decimator building block which has been realised in a 1.8μm CMOS double-poly technology, and achieves a frequency decimation capability from 16.59MHz to 5.53MHz with a total power consumption of only 1.75 mW. The experimental evaluation of the resulting performance behavior has been carried-out not only with respect to the non-ideal characteristics of the amplifiers but also with respect to the errors which may occur associated with the switch timing controlling the operation of the circuit.