Method of PLA´s Implementation : The Monoplane PLA

This paper presents several techniques for optimizing large monoplane PLAs (which contain mixed I/O lines). The different approaches used to optimize the area of these PLAs involve several VLSI topological optimization strategies. Compaction by cutting and reorganizing the product-term lines in order to reduce the number of rows in the entire PLA, is the main approach. The layout generation of an optimized monoplane PLA is adapted to its particular topology and involves an optimal distribution of ground refresh busses; the PLA cell optimization; I/O drivers optimization; and finally the entire PLA assembly.