DocumentCode
516443
Title
Testability of a VLSI Systolic Array
Author
Moore, W.R. ; Bawa, V
Author_Institution
Department of Electronics & Information, Engineering, University of Southampton, S09 5NH, UK; Consultant to GEC Research Limited
fYear
1985
fDate
16-18 Sept. 1985
Firstpage
271
Lastpage
276
Abstract
A test strategy is described for a recent bit-level systolic array design. The test vectors are simple, being only of order n for an nxn array, and comparators on or off the chip compress the results into pass/fail signals.
Keywords
Circuit testing; Clocks; Delay; Design engineering; Electronic equipment testing; Latches; Logic arrays; Logic testing; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European
Conference_Location
Toulouse, France
Type
conf
Filename
5468108
Link To Document