• DocumentCode
    516509
  • Title

    Automatic Generation of CMOS Layout Cells Under Topological Constraints

  • Author

    Piguet, C. ; Dijkstra, E. ; Berweiler, G.

  • Author_Institution
    Centre Suisse d´´Electronique et de Microtechnique S.A., Neuchâtel, Switzerland
  • fYear
    1986
  • fDate
    16-18 Sept. 1986
  • Firstpage
    68
  • Lastpage
    70
  • Abstract
    A program which generates gate matrix layout cells under user´s topological constraints is presented. This is a first step towards a very efficient module generator, i.e. a generator in which all slices and cells are assembled by abutment.
  • Keywords
    Assembly; CMOS technology; Circuits; Design methodology; Flip-flops; Libraries; Logic design; Shape; Topology; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European
  • Conference_Location
    Delft, The Netherlands
  • Type

    conf

  • Filename
    5468295
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516509