Design of a PLU (Programmable Logic Unit), a new block for signal processing

In this paper a new building block is described which can be used in Digital Signal Processing (DSP) IC´s. This module, the PLU (Programmable Logic Unit), can perform dyadic operations (A v B, A ^ B, A © B ...), monadic operations (¿A, ¿B , pass shiftr, ...) and bitwise operations (mask, scramble, ...). Furthermore, bitwise operations can be combined with monadic or dyadic operations. The PLU is easy to program as it is possible for users to define their own instruction set. In addition it is very effective with respect to area and speed. In order to make a flexible PLU, a parametrised module generator has been written. For a typical instance the total chip area necessary for an 8 bits PLU is 0.16 mm² in a 1.6 ¿m process. The delay of the PLU equals a two gate propagation delay.