DocumentCode
516668
Title
A CMOS Floating-Point Processing Chip for Verified Exact Vector Arithmetic
Author
Kernhof, Juergen ; Baumhof, Christoph ; Höfflinger, Bernd ; Kulisch, Ulrich ; Kwee, Steve ; Schramm, Peter ; Selzer, Manfred ; Teufel, Thomas
Author_Institution
Institute for Microelectronics Stuttgart, Allmandring 30a, 70569 Stuttgart (Germany)
fYear
1994
fDate
20-22 Sept. 1994
Firstpage
196
Lastpage
199
Abstract
A 33 MHz CMOS floating-point coprocessor which computes the vector scalar product without rounding errors has been designed. Using a floating-point algorithm for verified numerical computation, an ultra-high accuracy for double-precision operations is achieved with a 4k-bit fixed-point accumulator. This new type of accumulation is composed of a dual-port RAM and a fast carry acceleration logic. A peak performance of 15 MFLOPs in scalar product operations has been attained by the use of parallel operations. The 45k gate chip has been fabricated with the semicustom GATE FOREST [1].
Keywords
Acceleration; Application specific integrated circuits; CMOS process; Clocks; Coprocessors; Floating-point arithmetic; Hardware; Logic; Microprocessors; Roundoff errors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1994. ESSCIRC '94. Twentieth European
Conference_Location
Ulm, Germany
Print_ISBN
2-86332-160-9
Type
conf
Filename
5468499
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