A low power, 100 MHz 12 Ã\x97 18 + 30-b Multiplier-Accumulator operating in asynchronous and synchronous modes

A 12 × 18 bit parallel multiplier accumulator running at up to 100 MHz, operating in asynchronous or synchronous mode and with an optimized power consumption is presented. It has been designed in a CMOS 05 ¿m CNET / SGS Thomson technology. The multiplier has been designed using the differential cascode voltage switch logic. As the main drawback of the DCVS logic is its power consumption, an optimization procedure to minimize the speed-power trade-off of the DCVSL cells is proposed. It leads to an increase of 100 % in terms of speed and less than 45 % in terms of power consumption compared to conventional CMOS logic. In order to take advantage of the capability of DCVS logic to efficiently implement an asynchronous interface, a specific controller has been designed to make it possible to use the multiplier-accumulator in both synchronous and asynchronous environments.