DocumentCode
516687
Title
Low-Power Strategies for High-Performance CMOS Circuits
Author
Noll, Tobias G.
Author_Institution
University of Technology RWTH Aachen, Rogowski-Institute of Electrical Engineering, Schinkelstr. 2, D-52062 Aachen, Germany. tgn@rog.rwth-aachen.de
fYear
1994
fDate
20-22 Sept. 1994
Firstpage
72
Lastpage
83
Abstract
Power dissipation has become one of the most critical CMOS design parameters. It will be shown that even under constraints on the supply voltage there are effective strategies for the reduction of power dissipation on the different levels of the CMOS design process. Enforcing localization, using redundant number representations and applying an optimal degree of pipelining will be demonstrated as the most attractive strategies.
Keywords
CMOS process; CMOS technology; Capacitance; Clocks; Frequency; Power dissipation; Process design; Short circuit currents; Throughput; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1994. ESSCIRC '94. Twentieth European
Conference_Location
Ulm, Germany
Print_ISBN
2-86332-160-9
Type
conf
Filename
5468525
Link To Document