Title :
Basic Design Methods for CMOS Logic Circuits with Ordered Layout
Author :
Zahnd, J. ; Stauffer, A.
Author_Institution :
Ecole polytechnique fédérale de Lausanne, Laboratoire de systÿmes logiques, Lausanne, Switzerland
Abstract :
Methods are presented for synthesizing CMOS circuits from functional logic specifications (truth tables), without using intermediate logic diagrams. They are orientated towards a particular layout structure, described in [1], but can be easily extended to any other structure.
Keywords :
Boolean algebra; CMOS logic circuits; Circuit synthesis; Combinational circuits; Design methodology; Equations; Input variables; Logic design; Network synthesis; Pulse inverters;
Conference_Titel :
Solid-State Circuits Conference, 1983. ESSCIRC '83. Ninth European
Conference_Location :
Lausanne, Switzerland
Print_ISBN :
2-88074-021-5
