• DocumentCode
    516889
  • Title

    Automatic Generation of Metal Oriented Layout for CMOS Logic

  • Author

    Piguet, C. ; Bertarionne, M.

  • Author_Institution
    Centre Electronique Horloger S.A., Neuchâtel, Switzerland
  • fYear
    1983
  • fDate
    21-23 Sept. 1983
  • Firstpage
    167
  • Lastpage
    170
  • Abstract
    In order to decrease the development time and cost of integrated CMOS circuits, we present a design methodology based on the following characteristics: - direct translation of logic equations into symbolic layout - metal oriented symbolic layout - automatic generation of layout based on the assembly of microcells.
  • Keywords
    Automatic logic units; CMOS logic circuits; Character generation; Design automation; Design methodology; Equations; Layout; Logic design; MOSFETs; Microcell networks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1983. ESSCIRC '83. Ninth European
  • Conference_Location
    Lausanne, Switzerland
  • Print_ISBN
    2-88074-021-5
  • Type

    conf

  • Filename
    5468897
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516889