(MI)2 L: Multiinput-Multioutput Integrated Injection Logic

The (MI)²L structure will be discussed, which is a combination of CHL/CHIL and I²L, taking advantage of ion implantation. It provides improved speed-power product and functional density compared to conventional I²L schemes. The gate consists of a lateral npn transistor with intermediate collectors and a Schottky-inverter. The device fabrication is fully compatible with standard bipolar processes for analog circuits. The approach is applied to standard bipolar process of 6 ¿m epi-thickness and 35 V breakdown voltage. The results obtained are a minimum power-delay product of .07 pJ and a minimum delay of 15 ns at .38 pJ. The improved device parameters, packing density and design flexibility are discussed with the experimental results of test circuits, including a D-type frequency divider and MS flip-flop.