• DocumentCode
    516997
  • Title

    A Single 5 V, 65 ns, 16 pin, 16-kbit Dynamic N-MOS RAM

  • Author

    Itoh, K. ; Hori, R. ; Shimohigashi, K. ; Tominaga, Y.

  • Author_Institution
    Central Res. Lab., Hitachi, Ltd., Tokyo, Japan
  • fYear
    1978
  • fDate
    18-21 Sept. 1978
  • Firstpage
    103
  • Lastpage
    105
  • Abstract
    A single 5 V, 65 ns, 16 pin, 16-kbit dynamic N-MOS RAM is presented. A chip size of 3.18 × 4.96 nm2 and a power consumption of 215 mW for a 200 ns cycle time are realized with 3 μm photolithography, unique sense circuitry and on-chip biasing technique.
  • Keywords
    MOS memory circuits; photolithography; power supply circuits; random-access storage; bit rate 16 kbit/s; chip size; dynamic N-MOS RAM; on-chip biasing technique; photolithography; power consumption; size 3 mum; time 65 ns; unique sense circuitry; voltage 5 V; Circuits; Costs; DRAM chips; Energy consumption; Lithography; Power dissipation; Preamplifiers; Random access memory; Read-write memory; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference - Digest of Technical Papers, 1978. ESSCIRC 78. 4th European
  • Conference_Location
    Amsterdam
  • Type

    conf

  • Filename
    5469030
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516997