DocumentCode
517007
Title
High Speed Multiplication using ECL Gate Arrays
Author
Hollock, S. ; Gosling, J.B.
Author_Institution
Centre, Plessey Co. Ltd., Towcester, UK
fYear
1978
fDate
18-21 Sept. 1978
Firstpage
70
Lastpage
72
Abstract
An expandable multiplier chip has been designed on an ECL gate array using a novel serial-parallel algorithm. Systems applications of these devices will offer 64 × 64-bit multiplication in 140 nsecs plus a reduction in chip count over conventional systems.
Keywords
logic arrays; logic gates; ECL gate arrays; expandable multiplier chip; high speed multiplication; serial-parallel algorithm; time 140 ns; Algorithm design and analysis; Application software; Circuits; Clocks; High performance computing; Logic arrays; Magnetic resonance imaging; Propagation delay; Routing; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference - Digest of Technical Papers, 1978. ESSCIRC 78. 4th European
Conference_Location
Amsterdam
Type
conf
Filename
5469040
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