DocumentCode
517040
Title
A Standardized Method Reduces Design Time of C-MOS Integrated Circuits and Enables Automatic Checking
Author
Bertails, J.C. ; Zirphile, J.
Author_Institution
Div. Sescosem, Thomson-CSF, St. Egreve, France
fYear
1976
fDate
21-24 Sept. 1976
Firstpage
82
Lastpage
83
Abstract
A method based on a specific implantation associated with an effort of standardization allows to greatly simplify C-MOS integrated circuit design and checking. In spite of a drastic reduction in the number of the different elementary constituents used, realized circuits exhibit excellent characteristics without prohibitive increase of the chip area.
Keywords
CMOS integrated circuits; integrated circuit design; CMOS integrated circuit checking; CMOS integrated circuit design; automatic checking; elementary constituents; Aluminum; Circuit synthesis; Costs; Design methodology; Graphics; Integrated circuit interconnections; Libraries; Logic design; Standardization; VHF circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference, 1976. ESSCIRC 76. 2nd European
Conference_Location
Toulouse
Type
conf
Filename
5469083
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