• DocumentCode
    517045
  • Title

    Low-Power D-MOS Logic

  • Author

    Declercq, M. ; Laurent, Th

  • Author_Institution
    Lab. de Microelectron., Univ. Catholique de Louvain, Louvain-Ia-Neuve, Belgium
  • fYear
    1976
  • fDate
    21-24 Sept. 1976
  • Firstpage
    68
  • Lastpage
    70
  • Abstract
    A simple silicon-gate D-MOS process suitable for enhancement-depletion logic is described. Design and performance of D-MOS logic circuits are investigated and compared to standard E/D logic. Practical results of a low-power ring oscillator are presented.
  • Keywords
    MOS logic circuits; low-power electronics; oscillators; silicon; Si; enhancement-depletion logic; low power D-MOS logic; low-power ring oscillator; silicon-gate D-MOS process; standard E-D logic; Driver circuits; Inverters; Logic circuits; Logic design; Ring oscillators; Scattering parameters; Silicon; Transconductance; Transfer functions; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference, 1976. ESSCIRC 76. 2nd European
  • Conference_Location
    Toulouse
  • Type

    conf

  • Filename
    5469088
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=517045