Title :
A Review on Random Access MOS Memories
Author_Institution :
Siemens AG, data processing division, Munich, Germany
Abstract :
The progress achieved internationally in the field of MOS-RAM devices for EDP main memories is described in this paper. Under the continuous pressure to cut costs, storage density and capacity have been increased by a factor of 20 since 1969 so that memory technology has become the pacemaker for large scale integration. Improvements in the readout technique are discussed by taking the 4096 bit memory device Siemens S193 as an example. A more efficient peripheral circuitry, such as internal clock generation, TTL-compatible interface, dynamic address decoders and an integrated output amplifier make it easier for the user to employ these modern components. A number of unavoidable compromises in testing and encapsulation of the devices and in circuit simulation and optimization are dealt with. After a brief review of other storage principles a forecast of the development of dynamic MOS memories is given in conclusion.
Keywords :
Circuit simulation; Circuit testing; Clocks; Costs; Decoding; Integrated circuit technology; Large scale integration; Pacemakers; Random access memory; Timing;
Conference_Titel :
Solid State Circuits Conference (ESSCIRC), 1975 First European
Conference_Location :
Canterbury, UK
Print_ISBN :
0-85296-149-9